The invention relates to a switching circuit for regulating the repetition rate of clock pulses; these pulses determine the sampling times of a data signal transmitted from a data transmitter to a data receiver. The clock pulses, which are produced by a clock pulse generator, have a repetition rate which depend upon a control signal applied to the clock pulse generator.
The regulation of the sampling time of synchronously transmitted data during its transmission from a data transmmitter to a data receiver greatly influences transmission quality. The demands made on the regulation of the repetition rate of the clock pulses are the more exacting, the higher the data signalling rate for a given bandwidth. At the same time, however, with increase in data signalling rate, there are also greater unavoidable variations of group delay and transmission loss. Consequently, an impairment in transmission quality results, in particular when passing from binary to multistage transmission.
To regulate the repetition rate of clock pulses as a function of a control signal, the use of a circuit has been disclosed in the prior art wherein an oscillator signal is applied to an input of a frequency divider. The frequency divider has a division ratio which varies as a function of a control signal applied to it; the output of the frequency divider supplies clock pulses. The circuit of the invention, however, comprises a regulation circuit to which an input signal and the clock pulses are applied and which generates the control signal in such a way that the clock pulses and the input signal have the same repetition rate and the same phase. If the input signal consists of a data signal received in a data receiver, the data signal can be sampled with the aid of the clock pulses.